What is Aldec Active-HDL?
The Active-HDL software is a field-programmable gate array (FPGA) design creation and simulation development environment that is team-based. The software is made for Windows systems, with an IDE (Integrated Design Environment) that has HDL, graphic design suite, and RTL/gate-level simulator with mixed-language. The software has more than 120 EDA and FPGA tools for design, simulation, synthesis, and implementation processes. It also supports FPGA devices from Altera, Atmel, Lattice, Microsemi, Quicklogic, Xilinx, and others.
A main feature of the software includes project management that maintains uniformity and configures flow manager interfaces. It also includes graphical and text design entry for aid in the design process using text, schematic, and state machine, and also enables the distribution and delivery of IPs using more secure and reliable Interoperable Encryption standard. There are also simulations and debugging: a kernel mixed language simulator supporting VHDL, Verilog, SystemVerilog (Design), and SystemC; graphical debugging and code quality tools; metric driver verification that identifies unexercised parts of a design by means of coverage analysis tools; bug identification using ABV (Assertion-Based Verification) for SVA, PSL, and OVA; gap connection between HDL simulation and high level mathematical modeling environment for DSP blocks via MATLAB/Simulink interface. Also included in the software is an auto-generating Design Documentation in HTML and PDF.
File types supported by Aldec Active-HDL
Our users primarily use Aldec Active-HDL to open these file types: